The devutils library

Labs

Explore concepts through reproducible experiments.

Available labs

Further labs will build on the first gate workbench. Their purpose is to let you change a model, compare expected results and understand its limits.

  • Logic gate simulator — planned
  • 8-bit ALU in Verilog — planned
  • RISC-V emulator — planned
  • Cache visualizer — planned
  • Virtual memory walkthrough — planned
  • CMOS inverter simulation — planned

Before experimenting

Start with the truth tables in the Boolean-algebra article. A future simulator must distinguish its logical results from measurements of a physical circuit.

Arithmetic logic unit

Combine a four-bit adder, Boolean functions and selection; distinguish unsigned carry from signed overflow and connect computation to storage.

Binary adders

Derive a full adder, follow carries through four bits, and distinguish unsigned carry from signed overflow.

Boolean algebra

Describe two-state decisions with AND, OR and NOT, then connect the expressions to switching circuits.

Combinational logic

Specify a function, build it from gates, and verify a selector without confusing logic with timing.

Finite-state machines

Design a serial pattern detector, preserve overlapping matches, encode its states and verify every short input stream.

Logic gates

Turn Boolean operations into connected components, and distinguish a logical result from an electrical implementation.

Memory and registers

Separate holding a value from computing one, then organize stored bits into registers and addressed words.

Sequential logic

Combine stored state with a next-state function, trace a counter, and account for the time between clock edges.

Mathematical reasoning

Read variables, evaluate a rule and distinguish an example, a counterexample and a proof.

Models and abstraction

State what a model promises, trace its predictions and identify where its assumptions stop applying.

Signals and states

Separate a physical signal from the discrete state it represents, then read a simple time trace.

Units and scale

Keep units in a calculation, convert powers of ten and distinguish a duration from a rate.

RTL and hardware description

Describe a registered four-bit accumulator in Verilog, separate combinational wiring from clocked storage and trace simultaneous state updates.

Static timing analysis

Calculate setup and hold slack for a clocked path, derive the effect of skew and distinguish timing constraints from functional simulation.

Synthesis and technology mapping

Lower a circuit description into connected implementation cells, reason about Boolean equivalence and account for resource sharing without changing cycle behavior.