Laboratoires

Predict and verify AND, OR, NOT and XOR with two inputs and complete truth tables.

Compter les combinaisons de bits, convertir un entier non signé et distinguer un motif binaire du message qu’il représente.

Définir ce qu’un modèle garantit, vérifier ses hypothèses et comprendre pourquoi une table logique ne suffit pas à valider un circuit réel.

Lire une formule, définir ses entrées et distinguer un exemple, un contre-exemple et une preuve, avec exercices corrigés.

Distinguer tension, bit et message ; lire des seuils, des échantillons et une garantie de délai dans un modèle pédagogique corrigé.

Convertir secondes, millisecondes et microsecondes, additionner des durées et distinguer temps écoulé et débit avec des exercices corrigés.

Count protons, neutrons and electrons, distinguish isotopes from ions, and explain the energy sign of a covalent bond.

Count shared atoms in cubic cells, scale a repeating volume and distinguish vacancies, substitutions and interstitials.

Derive a sample resistance from resistivity and shape, convert areas correctly, and evaluate several material requirements together.

Explain n-type and p-type silicon, count dopants and derive a scoped compensation approximation without confusing carriers with net charge.

Count shared bonds, derive the SiO2 atom ratio and distinguish substrate silicon from an electrically insulating oxide.

Distinguish MMIO from RAM, calculate burst payload rate and reason about arbitration, ordering and completion.

Map byte addresses into a direct-mapped cache, reproduce a miss trace and calculate access-time and write-policy consequences.

Compare data-parallel execution, lane utilization and scoped scaling limits using end-to-end work and traffic.

Execute a complete eight-bit teaching program, trace wraparound and branches and connect state changes to a datapath.

Distinguish instruction semantics from hardware organization, read RV32I state and compare scoped execution-time models.

Trace pipeline stages, distinguish latency from throughput and budget stalls without changing architectural behavior.

Combine a four-bit adder, Boolean functions and selection; distinguish unsigned carry from signed overflow and connect computation to storage.

Derive a full adder, follow carries through four bits, and distinguish unsigned carry from signed overflow.

Describe two-state decisions with AND, OR and NOT, then connect the expressions to switching circuits.

Specify a function, build it from gates, and verify a selector without confusing logic with timing.

Design a serial pattern detector, preserve overlapping matches, encode its states and verify every short input stream.

Turn Boolean operations into connected components, and distinguish a logical result from an electrical implementation.

Separate holding a value from computing one, then organize stored bits into registers and addressed words.

Combine stored state with a next-state function, trace a counter, and account for the time between clock edges.

Trace accepted values, preserve pending data and separate interface throughput, latency, buffering and clock-domain assumptions.

Compare logic-level guarantees, calculate RC settling and distinguish physical waveforms from logical interpretations.

Apply current and voltage balance, calculate divider loading and reconcile power in a DC network.

Include the probe in the circuit, estimate measurement loading and separate resolution, accuracy and repeatability.

Calculate conductor resistance and clearance, follow return currents and distinguish connectivity checks from performance.

Reconcile regulator power, calculate capacitor droop and explain why effective capacitance and connection impedance matter.

Trace an explicit netlist, map electrical pins to physical pads and understand the scope of schematic checks.

Compare propagation with edge time, calculate first load reflections and distinguish incident-wave amplitude from source voltage.

Follow device/CPU buffer ownership, calculate fill intervals and preserve FIFO capacity while separating coherence from ordering.

Connect loader, kernel, hardware description and user space, then budget independent storage/RAM models and reason about recovery.

Budget event-to-handler latency, separate device flags from controller state and preserve driver lifetime across concurrent completion paths.

Connect bare-metal code to specified registers, distinguish read/write and W1C behavior and separate volatile from synchronization.

Trace a preemptive schedule, calculate scoped response times and distinguish utilization, blocking and synchronization.

Explain the path to main, budget RAM and vectors and distinguish image loading, authenticity and recovery policy.

Understand LUTs, registers and dedicated resources, compare a scoped cost model and separate configuration from fabrication.

Turn a netlist into geometry, calculate utilization and wiring effects, and distinguish connectivity, geometry and timing checks.

Describe a registered four-bit accumulator in Verilog, separate combinational wiring from clocked storage and trace simultaneous state updates.

Build an independent oracle, distinguish exhaustive scope from coverage and understand bounded formal and equivalence checks.

Calculate setup and hold slack for a clocked path, derive the effect of skew and distinguish timing constraints from functional simulation.

Lower a circuit description into connected implementation cells, reason about Boolean equivalence and account for resource sharing without changing cycle behavior.

Distinguish electrical quantities and calculate current, power and transferred energy in an ideal resistor circuit.

Read the direction of an electric force and calculate a simple induced voltage from a changing magnetic flux.

Balance electrical input, heat leaving a system and stored energy without confusing watts, joules and temperature.

Distinguish probability from amplitude and calculate energy differences in a three-level teaching model.

Connect a repeating crystal model to allowed electron energies, then distinguish a band diagram from a conductivity prediction.

Build an inverter and NAND, separate settled states from transitions and account for capacitive switching energy.

Calculate geometric density and dynamic-power ratios without equating transistor count with speed or efficiency.

Distinguish a continuous junction law from a constant-drop approximation and reconcile circuit power.

Distinguish leakage paths, compute standby energy and compare clock gating, sleep and task energy.

Use source-relative gate voltages, distinguish threshold from low resistance and solve a scoped switch circuit.

Explain equilibrium, fixed space charge and bias, then balance depletion widths in an abrupt-junction model.

Track a film through deposition and mask transfer, calculate a cycle-based thickness and budget underlayer and mask loss.

Separate dose from concentration, follow a uniform-profile counting model and distinguish retained dopants, activation and mobile carriers.

Read electrical connectivity across levels, follow damascene-style fill and CMP, and calculate a line-and-via resistance model.

Trace positive and negative resist, distinguish a resist opening from a material etch, and calculate a simple overlay margin.

Separate die and package tests, multiply stage fractions with the right denominators and reason about multi-die assembly assumptions.

Follow an ingot into wafer form, distinguish wafer, die and package, and read process changes in top view and cross-section.